Bipolar transistors are generally known as semiconductor components. A brief overview of the diverse methods for the production of bipolar transistors is given in the journal article “Advances in Bipolar VLSI” by George R. Wilson in Proceedings of the IEEE, Vol. 78, No. 11, 1990, pp. 1707 to 1719.
A standard process for the production of bipolar transistors is described in more detail below. Firstly, a subcollector zone, also referred to as a buried layer, is indiffused into a p-doped semiconductor substrate, by means of which zone the collector bulk resistance of the transistor can be effectively reduced. The semiconductor substrate is subsequently coated with an epitaxial n-conducting layer. Electrically insulated regions are then separated off in the epitaxial layer. These so-called epitaxial islands are isolated by means of reverse-biased pn junctions created by deeply indiffused p-type zones. This is followed by further diffusion steps used to define the base and emitter regions of the NPN bipolar transistor. The contact connection for the transistor terminals is subsequently performed.
DE 198 44 531 A1 describes a simplified method for the production of semiconductor components, in particular bipolar transistors, in which an epitaxy and isolation process as in the standard bipolar process is no longer required. The simplified method is distinguished by the fact that a mask is applied to the semiconductor substrate, which mask defines a window delimited by a circumferential edge, and an n-doped or p-doped well is produced by means of high-voltage ion implantation in the semiconductor substrate. The high-voltage ion implantation is effected with an energy high enough such that a p-doped or n-doped inner zone remains at the surface of the semiconductor substrate, while the edge zone of the n-doped or p-doped well reaches as far as the surface of the substrate. Proceeding from this semiconductor structure, it is possible to produce both NPN and PNP transistors. DE 198 44 531 A1 proposes an implantation of phosphorus ions with an implantation energy of 6 MeV.
Conventional integrated bipolar transistors are vertical transistors, that is to say that the collector-emitter current flows perpendicular to the wafer surface. Since the lateral dimensions are usually much greater than the vertical dimensions, the transistor can initially be reduced to a one-dimensional component. In the turned-off transistor, the applied voltage is dropped across the collector-base depletion layer. It must therefore be designed for the highest possible breakdown voltages. The field lines are likewise oriented perpendicular to the wafer surface. Under an applied reverse voltage, the majority charge carriers are withdrawn on both sides of the pn junction, which gives rise to a zone that is depleted of mobile charge carriers (depletion zone). The stationary negatively charged acceptors and the likewise stationary positively charged donors remain in said zone, so that a space charge arises which builds up an electric field. Therefore, the depletion zone is also called space charge zone. As the reverse voltage increases, the space charge rises on both sides of the pn junction, and thus the field strength rises as well. The local field strength E(x) is obtained by integration of the space charge from an edge x1 of the space charge zone to the depth x divided by the dielectric constant.
                              E          ⁡                      (            x            )                          =                              ∫                          x              1                        x                    ⁢                                                    q                ·                                  [                                                                                    N                        D                                            ⁡                                              (                                                  x                          ′                                                )                                                              -                                                                  N                        A                                            ⁡                                              (                                                  x                          ′                                                )                                                                              ]                                                                              ɛ                  0                                -                                  ɛ                  Si                                                      ⁢                                                  ⁢                          ⅆ                              x                ′                                                                        (        1        )            
Since the space charge zone is depleted of majority charge carriers, the space charge results from the product of the elementary charge q and the difference between the (volume) concentrations of the donors ND and the acceptors NA. The negatively charged acceptors are predominant on the p-doped side and the positively charged donors are predominant on the n-doped side. Owing to the neutrality condition, the charges on both sides of the pn junction must be identical in terms of magnitude.
The voltage V present at the pn junction is obtained by the integration of the field strength over the space charge zone.
                    V        :=                              ∫                          x              1                                      x              2                                ⁢                                    E              ⁡                              (                                  x                  ′                                )                                      ⁢                                                  ⁢                          ⅆ                              x                ′                                                                        (        2        )            
In this case, the integration limits x1 and x2 correspond to the edges of the space charge zone.
An avalanche breakdown takes place starting from a specific material- and doping-dependent field strength EDB, which is between 150-1000 kV/cm in the case of silicon. In order to achieve a high reverse voltage without exceeding the breakdown field strength EDB, a specific minimum depth and a suitable doping profile for the collector are required. In conventional transistors, the breakdown voltage between base and collector UCB0 is limited by the depth of the collector doping and the doping profile thereof. Since dopings several micrometers deep are not only complicated to produce and difficult to connect from the surface but also lead laterally to large structures and thus require much valuable chip area, integrated bipolar transistors have only a very limited dielectric strength. This circumstance is exacerbated by the fact that with an open base, a collector-emitter breakdown (UCE0 breakdown) already takes place at a significantly lower voltage UCE0 (<<UCB0). It results from the fact that in regions having sufficiently high field strength thermally generated charge carriers are accelerated to a such a great extent that they have enough energy to generate further electron-hole pairs by knocking out further electrons from the bonds above the Si crystal (multiplication effect). If this happens in the space charge zone of the collector-base junction directly below the emitter-base junction, then it is possible, in the case of an NPN transistor, for the holes generated to flow away via the base into the emitter and act like a base current in-this case. The latter is re-emitted in the emitter as an electron current increased by the current gain B, which current, for its part, flows into the collector, where it is amplified again by the multiplication effect. The UCE0 breakdown thus arises as a result of a positive feedback.
The relationship between UCE0, UCB0 and current gain B can be described by the following equation:
                              U                      CB            ⁢                                                  ⁢            0                          :=                              U                          CB              ⁢                                                          ⁢              0                                                          B              +              1                        n                                              (        3        )            
The indications for the empirical parameter n read variously:                n=4        n=4 for NPN transistors and n=2 for PNP transistors        n=4 for NPN transistors and n=6 for PNP transistors        n=4 for n-type silicon and n=2 for p-type silicon or overall n=3 . . . 6.        
With the most frequently mentioned value of n=4 and a typical current gain of B=100, UCE0≈⅓*UCB0 is obtained. As the collector current increases, the breakdown voltage even decreases somewhat, so that the reliable operating range of a bipolar transistor generally extends only to approximately 5 V below UCE0.